Silicon carbide (SiC) has excellent physical properties, such as a wider band gap, a higher breakdown field intensity, and a larger saturation drift velocity of electrons, as compared with silicon (Si). Thus, use of SiC as the starting constitutive material makes it possible to fabricate a semiconductor device for use with an electrical power of high withstand voltage and low resistance exceeding the limits of Si. Further, similar to Si, SiC has such a characteristic to allow forming an insulating layer through thermal oxidation. Based on these, it is supposed to be possible to realize an insulated gate-type field effect transistor (hereinafter, MISFET, typically known as a MOSFET) with a high withstand voltage and a low on-resistance, in which use is made of a single crystal of SiC as the material. Numerous researches and developments directed to this device have been under path.
Further, SiC is known to have an excellent transient response characteristic, and can be used in a high frequency region exceeding 100 kHz. Thus, it can be used to fabricate a power IC with high frequency and high power density, which cannot be realized with Si. Such a performance is preferable for making a logic circuit into an IC, as well as the power IC.
As shown in FIG. 17, a conventional SiC MISFET includes a SiC substrate 21, a SiC semiconductor region 22 formed of a p-type epitaxial layer formed on the SiC substrate 21, n+ type source region 23 and drain region 24 formed in the SiC semiconductor region 22, a gate insulating layer 25 formed to extend over the source region 23 and the drain region 24 on a surface of the p-type SiC semiconductor region 22, a gate electrode 26 provided on the gate insulating layer 25, an insulating layer 27 formed on the surface of the SiC semiconductor region 22, and a source electrode 30 and a drain electrode 31 electrically connected to the source region 23 and the drain region 24, respectively, formed through openings (contact regions 28 and 29) provided in the insulating layer 27. For example, the size of the conventional SiC MISFET is: a gate length Lg (which is equal to a channel length herein; hereinafter, “gate length” and “channel length” are treated as having the same meaning) of 3 μm, a thickness of a gate oxide layer of 40 nm, and depths of the source and drain regions of 300 nm. In such a device, the respective sheet resistance of the source and drain regions, which is parasitic resistance, is about 13 kΩ per square. In the SiC MISFET, on-resistance can be reduced by two orders of magnitude as compared with a Si MISFET. The reduction of the on-resistance becomes an important factor for improvement in device performance.
Further, when a MISFET is to be fabricated, the fabrication is performed in a non-self alignment manner in a SiC process, as disclosed in Patent Literature 1. This is because, since a temperature of activation annealing performed after impurity ion implantation is higher (about 1,600° C.) than that in a Si process and the gate oxide layer is not resistant to such a high temperature treatment, the gate oxide layer and the gate electrode are formed through separate mask alignments after impurity region formation by the ion implantation.